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authorStefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>2017-08-16 14:53:25 +0100
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:28:53 +0800
commit46fe72556efe672c53fd593c44036550a91ce0c3 (patch)
treee51b1e58df1b2a8532adb943b0956b88b5b1552f /Documentation/devicetree/bindings/clock
parent699690ba51cff2af19840b4722f6a05b4be087c6 (diff)
dt-bindings: clock: Document S32V234 MC_CGM and MC_ME
Add DT bindings documentation for the upcoming S32V234 clk driver. Add s32v234-clock.h header, which is referred in MC_CGM documentation. Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt31
-rw-r--r--Documentation/devicetree/bindings/clock/s32v234-mc_me.txt16
2 files changed, 47 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt
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index 000000000000..d0d43e6ae597
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt
@@ -0,0 +1,31 @@
+* NXP S32V234 Clock Generation Modules (MC_CGMs)
+
+The SoC supports four Clock Generation Modules, which provide registers for
+system and peripherals clock source selection and division. See chapters 22
+("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry
+Module (MC_ME)") in the reference manual[1].
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible:
+ Should be:
+ - "fsl,s32v234-mc_cgm0" for MC_CGM_0
+ - "fsl,s32v234-mc_cgm1" for MC_CGM_1
+ - "fsl,s32v234-mc_cgm2" for MC_CGM_2
+ - "fsl,s32v234-mc_cgm3" for MC_CGM_3
+- reg:
+ Location and length of the register set
+- #clock-cells (only for MC_CGM_0):
+ Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock
+ specifiers allowed in the clocks property of consumers.
+
+Example:
+clks: mc_cgm0@4003c000 {
+ compatible = "fsl,s32v234-mc_cgm0";
+ reg = <0x0 0x4003C000 0x0 0x1000>;
+ #clock-cells = <1>;
+};
+
+[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM
diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt
new file mode 100644
index 000000000000..e9f4dcc3a257
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+++ b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt
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+* NXP S32V234 Mode Entry Module (MC_ME)
+
+See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the
+reference manual[1].
+
+Required properties:
+- compatible: Should be "fsl,s32v234-mc_me"
+- reg: Location and length of the register set
+
+Example:
+mc_me: mc_me@4004a000 {
+ compatible = "fsl,s32v234-mc_me";
+ reg = <0x0 0x4004A000 0x0 0x1000>;
+};
+
+[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM