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| author | Icenowy Zheng <icenowy@aosc.io> | 2019-07-13 11:46:28 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-07-22 08:33:20 +0200 |
| commit | c5ed9475c22c89d5409402055142372e35d26a3f (patch) | |
| tree | efaf374835ea7534a86b1996de7ec7a11cfd3b85 /Documentation/devicetree/bindings/clock | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
clk: sunxi-ng: v3s: add the missing PLL_DDR1
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
0 files changed, 0 insertions, 0 deletions