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authorChanwoo Choi <cw00.choi@samsung.com>2016-12-02 15:29:02 +0900
committerMyungJoo Ham <myungjoo.ham@samsung.com>2017-01-31 14:12:18 +0900
commitb513652443fc515ec90202d005230f2afee457ad (patch)
tree70db7c1263538af39250a788897d011f009fc032 /Documentation/devicetree/bindings/devfreq
parent924b9111a14f2c913782597d9d0795c67f1a6898 (diff)
PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433
This patch adds the detailed corrleation between sub-blocks and VDD_INT power line for Exynos5433. VDD_INT provided the power source to INT (Internal) block. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Diffstat (limited to 'Documentation/devicetree/bindings/devfreq')
-rw-r--r--Documentation/devicetree/bindings/devfreq/exynos-bus.txt14
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index d3ec8e676b6b..d085ef90d27c 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|--- FSYS
|--- FSYS2
+- In case of Exynos5433, there is VDD_INT power line as following:
+ VDD_INT |--- G2D (parent device)
+ |--- MSCL
+ |--- GSCL
+ |--- JPEG
+ |--- MFC
+ |--- HEVC
+ |--- BUS0
+ |--- BUS1
+ |--- BUS2
+ |--- PERIS (Fixed clock rate)
+ |--- PERIC (Fixed clock rate)
+ |--- FSYS (Fixed clock rate)
+
Example1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to