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authorAlexey Brodkin <abrodkin@synopsys.com>2016-02-19 15:35:52 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2016-04-26 18:26:45 +0300
commita1f8ebe5cf8421460ea5bdb6a9cc53ab50a35b50 (patch)
tree637ae5dd7a36b3881361ec3c67eb2a86207f0ebb /Documentation/devicetree/bindings/display/snps,arcpgu.txt
parent51dacf208988e5a2561d9b4b560cacc8a7f025e7 (diff)
drm: Add DT bindings documentation for ARC PGU display controller
This add DT bindings documentation for ARC PGU display controller. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-snps-arc@lists.infradead.org Acked-by: Rob Herring <robh@kernel.org>
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+ARC PGU
+
+This is a display controller found on several development boards produced
+by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
+framebuffer and sends it to a single digital encoder (usually HDMI).
+
+Required properties:
+ - compatible: "snps,arcpgu"
+ - reg: Physical base address and length of the controller's registers.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For ARC PGU it should contain:
+ - "pxlclk" for the clock feeding the output PLL of the controller.
+
+Required sub-nodes:
+ - port: The PGU connection to an encoder chip.
+
+Example:
+
+/ {
+ ...
+
+ pgu@XXXXXXXX {
+ compatible = "snps,arcpgu";
+ reg = <0xXXXXXXXX 0x400>;
+ clocks = <&clock_node>;
+ clock-names = "pxlclk";
+
+ port {
+ pgu_output: endpoint {
+ remote-endpoint = <&hdmi_enc_input>;
+ };
+ };
+ };
+};