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authorLiu Ying <victor.liu@nxp.com>2019-11-01 16:13:10 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 15:58:01 +0800
commit3f00d5aa73fdd2257b3d3a9ac782d54625c5446d (patch)
tree768497563a32302a9ce18e274fabcf94e5b2b155 /Documentation/devicetree/bindings/display
parentab29cdf8ae57ba00b79ddc40e00a31904d3a8804 (diff)
dt-bindings: display: fsl-imx-drm: Add DPR channel property to dpu binding doc
This patch adds DPR channel property to dpu binding doc. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
-rw-r--r--Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index 6bc9d2a432e2..2b91e53cd7f4 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -131,6 +131,8 @@ Required properties:
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
- power-domains: phandles pointing to power domain.
- power-domain-names: power domain names relevant to power-domains phandles.
+- fsl,dpr-channels: phandles to the DPR channels attached to this DPU,
+ sorted by memory map addresses.
Optional properties:
- port@[0-1]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
@@ -214,6 +216,9 @@ dpu: dpu@56180000 {
<&pd IMX_SC_R_DC_0_PLL_0>,
<&pd IMX_SC_R_DC_0_PLL_1>;
power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>;
dpu_disp0: port@0 {
reg = <0>;