diff options
| author | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2019-11-22 10:10:28 +0200 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:01:33 +0800 |
| commit | 8f09a3eeff6e70f2270f0828bd0b7a0c1806af5f (patch) | |
| tree | b8df990670bb6c70a7c03c67496fb6034a865ba2 /Documentation/devicetree/bindings/display | |
| parent | 76c17b70c9efc08e9e8f95720571599a1a5790ff (diff) | |
dt-bindings: display: imx8mq-dcss: add clocks needed for HDMI
This adds dt bindings for pll_src and pll_phy_ref, used when output is on HDMI.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml index efd24944b212..4ed240fe6d4e 100644 --- a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -47,6 +47,8 @@ properties: - description: RTRAM clock - description: Pixel clock, can be driver either by HDMI phy clock or MIPI - description: DTRC clock, needed by video decompressor + - description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI; + - description: PLL PHY reference clock, used when output is HDMI; clock-names: items: @@ -55,6 +57,8 @@ properties: - const: rtrm - const: pix - const: dtrc + - const: pll_src + - const: pll_phy_ref port@0: type: object @@ -71,8 +75,9 @@ examples: interrupt-names = "ctx_ld", "ctxld_kick", "vblank"; interrupt-parent = <&irqsteer>; clocks = <&clk 248>, <&clk 247>, <&clk 249>, - <&clk 254>,<&clk 122>; - clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + <&clk 254>,<&clk 122>, <&clk 266>, <&clk 267>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", + "pll_src", "pll_phy_ref"; assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; assigned-clock-rates = <800000000>, |