LF-842-1: drm/bridge: nwl-dsi: Change mipi clocks re-parenting

The MIPI clock parenting is made in dts file, causing the MIPI clocks to
be parented even if that specific MIPI node is needed or not, causing
issues to the LVDS block (which has a shared PHY with MIPI on 8QXP).
In order to avoid these problems with the shared PHY on 8QXP, store the
MIPI parent clock for phy and escape clocks, along with their rates and
do the re-parenting in the MIPI driver only when a bridge (or panel) is
attached to it.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
[Aisheng: Tested on MX8QM/QXP with single LVDS-HDMI or MIPI panel]
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>

(cherry picked from commit 2f794bb2f88e18e43dab31f2edea98177fce4e95)

0 files changed, 0 insertions, 0 deletions