diff options
| author | Liu Ying <victor.liu@nxp.com> | 2017-07-03 13:07:23 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:58:01 +0800 |
| commit | ab29cdf8ae57ba00b79ddc40e00a31904d3a8804 (patch) | |
| tree | de2b87c5a8e8703979f854e4c6a3f5070bd5062b /Documentation/devicetree/bindings/display | |
| parent | b76ebc473bac2170b944a8cee39cd17b62d0226b (diff) | |
dt-bindings: display: fsl-imx-drm: Add i.MX8 DPR(Display Prefetch Resolve) support
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds device tree
binding doc support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index e49598138f9d..6bc9d2a432e2 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -268,6 +268,37 @@ prg@56040000 { power-domains = <&pd IMX_SC_R_DC_0>; }; +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,<chip>-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as defined in + include/dt-bindings/firmware/imx/rsrc.h +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@560e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + Parallel display support ======================== |