diff options
| author | Troy Lee <troy_lee@aspeedtech.com> | 2020-12-07 17:00:11 +0800 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-12-07 12:03:11 +0100 |
| commit | e36a17f846bc9ebc540a6c53f38421a1b2dadfdb (patch) | |
| tree | 19aef7d49fb7c3dc6419e065ab76bee5e9023ea1 /Documentation/devicetree/bindings/edac | |
| parent | 0477e92881850d44910a7e94fc2c46f96faa131f (diff) | |
dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
Add Aspeed AST2400 and AST2600 binding for the Aspeed EDAC driver.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20201207090013.14145-1-troy_lee@aspeedtech.com
Diffstat (limited to 'Documentation/devicetree/bindings/edac')
| -rw-r--r-- | Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt index 6a0f3d90d682..8ca9e0a049d8 100644 --- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -1,6 +1,6 @@ -Aspeed AST2500 SoC EDAC node +Aspeed BMC SoC EDAC node -The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error correction check). The memory controller supports SECDED (single bit error correction, double bit @@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller. Required properties: -- compatible: should be "aspeed,ast2500-sdram-edac" +- compatible: should be one of + - "aspeed,ast2400-sdram-edac" + - "aspeed,ast2500-sdram-edac" + - "aspeed,ast2600-sdram-edac" - reg: sdram controller register set should be <0x1e6e0000 0x174> - interrupts: should be AVIC interrupt #0 |