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| author | Dan Carpenter <dan.carpenter@oracle.com> | 2016-01-20 12:54:51 +0300 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-01-25 11:17:14 +0100 |
| commit | 6f3508f61c814ee852c199988a62bd954c50dfc1 (patch) | |
| tree | d73bc72f9af1f1ad3521598a341ac14c7ba4d099 /Documentation/devicetree/bindings/edac | |
| parent | 92e963f50fc74041b5e9e744c330dca48e04f08d (diff) | |
EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
dct_sel_base_off is declared as a u64 but we're only using the lower 32
bits because of a shift wrapping bug. This can possibly truncate the
upper 16 bits of DctSelBaseOffset[47:26], causing us to misdecode the CS
row.
Fixes: c8e518d5673d ('amd64_edac: Sanitize f10_get_base_addr_offset')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: <stable@vger.kernel.org>
Link: http://lkml.kernel.org/r/20160120095451.GB19898@mwanda
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/edac')
0 files changed, 0 insertions, 0 deletions