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authorLuca Ceresoli <luca@lucaceresoli.net>2020-06-11 23:11:40 +0200
committerMoritz Fischer <mdf@kernel.org>2020-06-18 18:17:06 -0700
commit9d08b9ecbb2c7e0efa124e9a67715336ec0dd174 (patch)
tree1ab71856ff4464034d7639f8a2ddbf7e8e655439 /Documentation/devicetree/bindings/fpga
parent55dc9b87e4a8e4d0fb1b7169bab7e23d27ba4209 (diff)
dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
The Xilinx 7-series uses the same protocol, mention that. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/fpga')
-rw-r--r--Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt9
1 files changed, 6 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
index cfa4ed42b62f..9f103f3872e8 100644
--- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
+++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
@@ -1,11 +1,14 @@
Xilinx Slave Serial SPI FPGA Manager
-Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
-what is referred to as "slave serial" interface.
+Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
+bitstream over what is referred to as "slave serial" interface.
The slave serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
-See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+See:
+- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Required properties:
- compatible: should contain "xlnx,fpga-slave-serial"