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author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-08-17 19:48:42 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-08-17 19:48:42 +0200 |
commit | 9d9d90a9af5472e0698cc5fb7b2acc37e5837c95 (patch) | |
tree | e8647d20d1317556150fb08be046029ed427017a /Documentation/devicetree/bindings/iio | |
parent | 9caf92ab573fd83c7455b65d4eefcefc1a9d2188 (diff) | |
parent | d484c21bacfa8bd2fa9fc26393ec59108f508c4c (diff) |
Merge tag 'iio-for-5.15b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next
Jonathan writes:
2nd set of new IIO device support and cleanups for the 5.15 cycle.
A small pull request to pick up a few new drivers and some cleanup
and fix patches.
New device support
* ad5110 non-volatile digital potentiometer
- New driver
* renesas rzl/gl2 12-bit / 8 channel ADC block
- New driver and bindings
Minor or late breaking fixes and cleanups
* ltc2983
- Fix a false assumption of initial interrupt during probe().
* hp03
- Use devm_* to simplify probe and allow the remove function to be dropped.
* rockchip_saradc
- Use a regulator notifier to reduce overheads of querying the scale.
* tag 'iio-for-5.15b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio:
iio: adc: Add driver for Renesas RZ/G2L A/D converter
dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter
iio: pressure: hp03: update device probe to register with devm functions
iio: adc: rockchip_saradc: add voltage notifier so get referenced voltage once at probe
iio: ltc2983: fix device probe
iio: potentiometer: Add driver support for AD5110
dt-bindings: iio: potentiometer: Add AD5110 in trivial-devices
Diffstat (limited to 'Documentation/devicetree/bindings/iio')
-rw-r--r-- | Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml new file mode 100644 index 000000000000..c80201d6a716 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L ADC + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: | + A/D Converter block is a successive approximation analog-to-digital converter + with a 12-bit accuracy. Up to eight analog input channels can be selected. + Conversions can be performed in single or repeat mode. Result of the ADC is + stored in a 32-bit data register corresponding to each channel. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-adc # RZ/G2{L,LC} + - const: renesas,rzg2l-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: converter clock + - description: peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: presetn + - const: adrst-n + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + - reset-names + +patternProperties: + "^channel@[0-7]$": + $ref: "adc.yaml" + type: object + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + description: | + The channel number. It can have up to 8 channels numbered from 0 to 7. + items: + - minimum: 0 + maximum: 7 + + required: + - reg + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + adc: adc@10059000 { + compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; + reg = <0x10059000 0x400>; + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G044_ADC_PCLK>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_ADC_PRESETN>, + <&cpg R9A07G044_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; |