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author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-25 11:32:01 +0100 |
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committer | Marc Zyngier <maz@kernel.org> | 2020-12-11 14:47:49 +0000 |
commit | 47d5e0b0e1c151c06885a78a108001ead96adc75 (patch) | |
tree | fc6a151e1b7c7ff7712a70419ac124cde13e945e /Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | |
parent | 0b39498230ae53e6af981141be99f4c7d5144de6 (diff) |
dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201125103206.136498-2-gregory.clement@bootlin.com
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml new file mode 100644 index 000000000000..be82920f6798 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microsemi Ocelot SoC ICPU Interrupt Controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + the Microsemi Ocelot interrupt controller that is part of the + ICPU. It is connected directly to the MIPS core interrupt + controller. + +properties: + compatible: + items: + - enum: + - mscc,ocelot-icpu-intr + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + +additionalProperties: false + +examples: + - | + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; +... |