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authorAlban Bedel <albeu@free.fr>2015-05-31 01:52:28 +0200
committerRalf Baechle <ralf@linux-mips.org>2015-06-21 21:54:03 +0200
commitbb35586fd07447515deaa774c0aa07cdfa4d4743 (patch)
treec9ca257150ff9c617237f07ddef0bbe8ea9c42e1 /Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
parent0fa4af8f53d0d2149b75d1e00a395c63922495fb (diff)
DEVICETREE: Add bindings for the ATH79 MISC interrupt controllers
Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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+Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
+
+The MISC interrupt controller is a secondary controller for lower priority
+interrupt.
+
+Required Properties:
+- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
+ as fallback
+- reg: Base address and size of the controllers memory area
+- interrupt-parent: phandle of the parent interrupt controller.
+- interrupts: Interrupt specifier for the controllers interrupt.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+ source, should be 1
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+
+ interrupt-controller@18060010 {
+ compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
+ reg = <0x18060010 0x4>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };