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| author | Zhen Lei <thunder.leizhen@huawei.com> | 2020-09-24 15:17:52 +0800 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-09-25 16:49:15 +0100 |
| commit | 8156b80fd4885d0ca9748e736441cc37f4eb476a (patch) | |
| tree | daf899f195a15e2c19fc764f7b72d8fdaa31c289 /Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt | |
| parent | 54a38440b84f8933b555c23273deca6a396f6708 (diff) | |
dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller
Add the required updates to describe the use of dw-apb-ictl as a primary
interrupt controller.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
[maz: commit message]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200924071754.4509-5-thunder.leizhen@huawei.com
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt index 086ff08322db..2db59df9408f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt @@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl) Synopsys DesignWare provides interrupt controller IP for APB known as dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. +APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt +controller in some SoCs, e.g. Hisilicon SD5203. Required properties: - compatible: shall be "snps,dw-apb-ictl" @@ -10,6 +11,8 @@ Required properties: region starting with ENABLE_LOW register - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 + +Additional required property when it's used as secondary interrupt controller: - interrupts: interrupt reference to primary interrupt controller The interrupt sources map to the corresponding bits in the interrupt @@ -21,6 +24,7 @@ registers, i.e. - (optional) fast interrupts start at 64. Example: + /* dw_apb_ictl is used as secondary interrupt controller */ aic: interrupt-controller@3000 { compatible = "snps,dw-apb-ictl"; reg = <0x3000 0xc00>; @@ -29,3 +33,11 @@ Example: interrupt-parent = <&gic>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; }; + + /* dw_apb_ictl is used as primary interrupt controller */ + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; |