diff options
| author | Roger Quadros <rogerq@ti.com> | 2016-02-19 11:01:02 +0200 |
|---|---|---|
| committer | Roger Quadros <rogerq@ti.com> | 2016-04-15 11:55:06 +0300 |
| commit | b2bac25a4d298309bb4b2649bb1107ddaa287c47 (patch) | |
| tree | f8bf795b115860f570f179f3ee65ffa6b992a0a8 /Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | |
| parent | 210325f0f4eb531f83ffb0b0f95612e2a8063983 (diff) | |
memory: omap-gpmc: Support WAIT pin edge interrupts
OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered
interrupts if not used for memory wait state insertion.
Support these interrupts via the gpmc IRQ domain.
The gpmc IRQ domain interrupt map is:
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 edge
3 - GPMC_WAIT1 edge, and so on
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt index 97e71924dbbb..21055e210234 100644 --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt @@ -33,10 +33,13 @@ Required properties: As this will change in the future, filling correct values here is a requirement. - interrupt-controller: The GPMC driver implements and interrupt controller for - the NAND events "fifoevent" and "termcount". + the NAND events "fifoevent" and "termcount" plus the + rising/falling edges on the GPMC_WAIT pins. The interrupt number mapping is as follows 0 - NAND_fifoevent 1 - NAND_termcount + 2 - GPMC_WAIT0 pin edge + 3 - GPMC_WAIT1 pin edge, and so on. - interrupt-cells: Must be set to 2 - gpio-controller: The GPMC driver implements a GPIO controller for the GPMC WAIT pins that can be used as general purpose inputs. |