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authorSherry Sun <sherry.sun@nxp.com>2020-02-17 20:37:12 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2021-11-02 16:54:11 +0800
commitf8a9731ef4e40688543c5f2a7b060854e6a2b83d (patch)
treeb625f192d03d0e312284aeb9e6425366f28c2e7d /Documentation/devicetree/bindings/memory-controllers
parent8b9d0f0d9ff708bddec17d196b09a731f19107c1 (diff)
MLK-23333-1 dt: bindings: Document i.MX8MP DDRC in Synopsys documentation
Add information for i.MX8MP DDRC which reports the single bit errors that are corrected and the double bit errors that are detected. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> [ Aisheng: update to yaml format ] Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
index a24588474625..d4d5851cb981 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
@@ -12,13 +12,13 @@ maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
- The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
- 32-bit bus width configurations.
+ The ZynqMP and i.MX8MP DDR ECC controller has an optional ECC support in 64-bit
+ and 32-bit bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
- These both ECC controllers correct single bit ECC errors and detect double bit
+ These all ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
properties:
@@ -26,6 +26,7 @@ properties:
enum:
- xlnx,zynq-ddrc-a05
- xlnx,zynqmp-ddrc-2.40a
+ - fsl,imx8mp-ddrc
interrupts:
maxItems: 1