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| author | Thierry Reding <treding@nvidia.com> | 2017-06-26 17:33:12 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 12:42:30 +0100 |
| commit | f580fd3f9d78cf0425ab98950796c578d8a82167 (patch) | |
| tree | 5ab1276160226e5cae7291f12c822fcb9bec656a /Documentation/devicetree/bindings/memory-controllers | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
dt-bindings: misc: Add Tegra186 MISC registers bindings
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
0 files changed, 0 insertions, 0 deletions