diff options
| author | Joel Stanley <joel@jms.id.au> | 2018-02-20 12:13:28 +1030 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2018-02-20 17:41:30 +0100 |
| commit | 14b5057a2f84b9da246e5bda29c9fd914a8f691c (patch) | |
| tree | 05b7aef96fb0d59d6fff3e778935f664c17c4e35 /Documentation/devicetree/bindings/mfd | |
| parent | 320da785db9b724cc099c79852de477f390b6cab (diff) | |
dt-bindings: aspeed-lpc: Add reset controller
This describes the reset controller present in the LPC address space.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
[p.zabel@pengutronix.de: removed a space before tab in indent]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree/bindings/mfd')
| -rw-r--r-- | Documentation/devicetree/bindings/mfd/aspeed-lpc.txt | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..7136432f9905 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,3 +135,24 @@ lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + +LPC reset control +----------------- + +The UARTs present in the ASPEED SoC can have their resets tied to the reset +state of the LPC bus. Some systems may chose to modify this configuration. + +Required properties: + + - compatible: "aspeed,ast2500-lpc-reset" or + "aspeed,ast2400-lpc-reset" + - reg: offset and length of the IP in the LHC memory region + - #reset-controller indicates the number of reset cells expected + +Example: + +lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; +}; |