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authorAnsuel Smith <ansuelsmth@gmail.com>2021-10-14 00:39:12 +0200
committerVladimir Oltean <vladimir.oltean@nxp.com>2022-05-04 15:24:48 +0200
commite1e3ecac95603c99595c7d9f2a3b49db73b698a5 (patch)
tree755497c1f2a463d27319a401f2c95cd23852385b /Documentation/devicetree/bindings/net
parentd751889610b22cc323263764e8a64a091632e757 (diff)
dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 13ad5ccc093ff448b99ac7e138e91e78796adb48) Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/net')
-rw-r--r--Documentation/devicetree/bindings/net/dsa/qca8k.txt10
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index aeb206556f54..05a8ddfb5483 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -45,6 +45,16 @@ A CPU port node has the following optional node:
Mostly used in qca8327 with CPU port 0 set to
sgmii.
- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
+- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX
+ chain along with Signal Detection.
+ This should NOT be enabled for qca8327. If enabled with
+ qca8327 the sgmii port won't correctly init and an err
+ is printed.
+ This can be required for qca8337 switch with revision 2.
+ A warning is displayed when used with revision greater
+ 2.
+ With CPU port set to sgmii and qca8337 it is advised
+ to set this unless a communication problem is observed.
For QCA8K the 'fixed-link' sub-node supports only the following properties: