diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-08-23 13:18:28 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 17:05:21 +0800 |
| commit | 6d0d10f1bee40c4288c914c669e6fb96c31bd97f (patch) | |
| tree | fc651ce038d702e294a25abfee390b50cf655b86 /Documentation/devicetree/bindings/pci/layerscape-pci.txt | |
| parent | 3faa46a384e9b795b5f9fa697300be8ea4367c80 (diff) | |
dt-bindings: pci: layerscape-pci: Add a optional property big-endian
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/layerscape-pci.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f7f706ffe43f..4614ce591ae5 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -41,6 +41,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { |