diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2017-05-26 16:41:46 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 3ce2f046d086ce2eeea131427b81df3bd5ca243d (patch) | |
| tree | 07152c29ea80177de0958cc130614ea5c4ec52bc /Documentation/devicetree/bindings/pci | |
| parent | c64898abe3dbfc35cd11ec8cb2c2d682107e6f6f (diff) | |
MLK-15064-1 ARM: imx: pcie: enable imx8 pcie
- use one standalone hsio node to share the region to
pciea, pcieb and sata.
- axi master slave and dbi clks and pipe_clk are required
- enable pcieb
change the pd of the pcieb, otherwise, clk is failed to enable
- add the cpu addr offset
Bit[31:24]
pciea 60 - 6f ---> 40 - 4f
pcieb 70 - 7f ---> 80 - 8f
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 1f8db0b1ecef..6a3db76e4db7 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie", "fsl,imx8qm-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -35,6 +35,22 @@ Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: - "pcie_inbound_axi" +Additional required properties for imx8 pcie: +- hsio : should be <&hsio>. + The phandle points to the hsio region containing the hsio + such as the pcie and sata control registers. +- hsio-cfg: hsio configration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. +- ctrl-id: used to distinguish pciea or pcieb. + 0: pciea, 1: pcieb. +- cpu-base-addr: the base cpu address mapped from hsio address. + Example: + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; Example: pcie@0x01000000 { |