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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2016-08-09 19:30:09 +0530
committerRob Herring <robh@kernel.org>2016-08-30 17:07:47 -0500
commit9cbbae2a62bce72c17aeb204efeec240f45c4f4f (patch)
tree8cdc2df6dc58695bab731f4fc7c14ed223ddade7 /Documentation/devicetree/bindings/pci
parentc4dcd205ebabe730858fc0f33a6a9a09bcd53452 (diff)
PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
Updating device tree documentation with prefetchable memory sapce. Configuration space shifted to 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
-rw-r--r--Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 337fc97d18c9..3259798a1192 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 {
msi-parent = <&nwl_pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x0 0xe0000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
- ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
+ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
pcie_intc: legacy-interrupt-controller {
interrupt-controller;