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| author | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-30 14:59:53 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-30 14:59:53 +0800 |
| commit | 5865329eb17c89b85d689179ec233e0215a92548 (patch) | |
| tree | 5d2c5d68fd847219138ce9900da7ffe9d465de47 /Documentation/devicetree/bindings/pci | |
| parent | 8bb7eca972ad531c9b149c0a51ab43a417385813 (diff) | |
| parent | da26f94a2033cbac67e7154e3ad7e7008e2e13b9 (diff) | |
Merge remote-tracking branch 'origin/pcie/core' into pcie/next
* origin/pcie/core: (11 commits)
LF-3964-2 Revert "MLK-20684 PCI: Disable MSI on CYW4356 and CYW4359 chips"
LF-3964-1 Revert "MLK-20716 PCI: add quirk for cyw4356 to disable D3 mode"
LF-2681-2 misc: pci_endpoint_test: Add driver data for imx8 pcie controllers
misc: pci_endpoint_test: Add LX2162A in pci_device_id table
MLK-24012-11 misc: pci_endpoint_test: add the imx pcie ep device supports
...
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..a0ce177c9eb8 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -30,8 +30,12 @@ Required properties: - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. + ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -47,8 +51,9 @@ Example: reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */ + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */ + interrupt-names = "aer", "pme"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; |