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authorLiu Ying <victor.liu@nxp.com>2021-06-02 11:41:46 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2021-11-02 17:07:15 +0800
commitc5113d7749a4507a828e7052f1a49630b50e68c5 (patch)
treea947592fabdda224ecfb7ac0d1e11a9f1ae626a1 /Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
parent457d56f30decc98ed19fe220bea4f3e6ff6556df (diff)
MLK-25550-1 dt-bindings: phy: mixel,mipi-dsi-phy: Add compatible string for i.MX8ulp
This patch adds compatible string for Mixel MIPI DPHY embedded in i.MX8ulp SoC. Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Leo Li <leoyang.li@nxp.com> Cc: Sandor Yu <Sandor.yu@nxp.com> Cc: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt')
-rw-r--r--Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt3
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
index 9b23407233c0..f34ca4c759a8 100644
--- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
@@ -5,8 +5,9 @@ MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
electrical signals for DSI.
Required properties:
-- compatible: Must be:
+- compatible: Must be one of:
- "fsl,imx8mq-mipi-dphy"
+ - "fsl,imx8ulp-mipi-dphy"
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
- "phy_ref": phandle and specifier referring to the DPHY ref clock