MLK-15001-20 phy: Add Mixel LVDS PHY support

This patch adds Mixel LVDS PHY support.
This PHY supports two LVDS channels.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt
new file mode 100644
index 000000000000..27fb5a4c182d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt
@@ -0,0 +1,39 @@
+Mixel LVDS PHY
+
+This LVDS PHY supports two LVDS channels.
+
+Required properties:
+- compatible: must be "mixel,lvds-phy".
+- reg: offset and length of the register block.
+- #address-cells: number of address cells for the LVDS channel subnodes, must
+		  be <1>.
+- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be "phy".
+- power-domains: phandle pointing to power domain.
+
+The LVDS PHY device tree node should have the subnodes corresponding to the two
+LVDS channels. These subnodes must contain the following properties:
+- reg: the PHY ID.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
+
+Example:
+	ldb1_phy: ldb_phy@56241000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,lvds-phy";
+		reg = <0x0 0x56241000 0x0 0x100>;
+		clocks = <&clk IMX8QM_LVDS0_PHY_CLK>;
+		clock-names = "phy";
+		power-domains = <&pd_lvds0>;
+
+		ldb1_phy1: port@0 {
+			reg = <0>;
+			#phy-cells = <0>;
+		};
+
+		ldb1_phy2: port@1 {
+			reg = <1>;
+			#phy-cells = <0>;
+		};
+	};