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authorYunzhi Li <lyz@rock-chips.com>2015-01-21 18:26:00 +0800
committerKishon Vijay Abraham I <kishon@ti.com>2015-01-30 16:06:47 +0530
commit9b43e5ec89dd0c863959ae0157ad3d693588ab44 (patch)
tree336240a7c5612ba0d13e6d5105c87307802dc7db /Documentation/devicetree/bindings/phy
parent5402d927ae96bd1413ecc6bac966fd8b6d3b8159 (diff)
Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs found on Rockchip SoCs usb interface. Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt37
1 files changed, 37 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
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index 000000000000..826454ac43bb
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+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,37 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- #phy-cells: should be 0
+- reg: PHY configure reg address offset in GRF
+ "0x320" - for PHY attach to OTG controller
+ "0x334" - for PHY attach to HOST0 controller
+ "0x348" - for PHY attach to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names: string, clock name, must be "phyclk"
+
+Example:
+
+usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ };
+};