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| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 10:11:08 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-06-24 10:00:28 +0800 |
| commit | 1bda33273eccae3c0d878d34660eca9da1765db0 (patch) | |
| tree | 319e6e9093d8cdd45d9eb1359f0db343167562d0 /Documentation/devicetree/bindings/phy | |
| parent | 30f393c50b1ba2b1ddde847f280e724534a0a2fb (diff) | |
MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
0 files changed, 0 insertions, 0 deletions