diff options
author | Liu Ying <victor.liu@nxp.com> | 2019-02-19 11:18:25 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:45:13 +0800 |
commit | 824cbfa98d024b789bba9563698710bb0f98041c (patch) | |
tree | ca1a73129fe2e5a7ecc3e8e9600424b2b2e6c679 /Documentation/devicetree/bindings/phy | |
parent | 800275e78a8459ad59da84b90ea52d27dcb2af61 (diff) |
dt-bindings: phy: Add DT binding for Mixel LVDS PHY
This patch adds device tree binding for Mixel LVDS PHY,
as found in i.MX8qm SoC.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt new file mode 100644 index 000000000000..27d0d342c53d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt @@ -0,0 +1,39 @@ +Mixel LVDS PHY + +This LVDS PHY supports two LVDS channels. + +Required properties: +- compatible: must be "mixel,lvds-phy". +- reg: offset and length of the register block. +- #address-cells: number of address cells for the LVDS channel subnodes, must + be <1>. +- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +The LVDS PHY device tree node should have the subnodes corresponding to the two +LVDS channels. These subnodes must contain the following properties: +- reg: the PHY ID. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example: + ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; |