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authorJC Kuo <jckuo@nvidia.com>2019-02-21 16:46:34 +0100
committerKishon Vijay Abraham I <kishon@ti.com>2019-04-17 14:12:47 +0530
commitbbf711682cd570697086e88388a2c718da918894 (patch)
tree7198f3e76d8942c0b89e4dd9ee24b229fa09f04a /Documentation/devicetree/bindings/phy
parenta630d54dfa937a937e3faf172ca41b9bd2647c72 (diff)
phy: tegra: xusb: Add Tegra186 support
Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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