diff options
| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2018-03-12 13:25:40 +0800 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2018-03-16 13:40:43 +0530 |
| commit | c55fbcb8cf6b3653103f046232ada503e482b57d (patch) | |
| tree | 8ea3a697bbd0a1f0f6e9aab01d167c0041f5a70c /Documentation/devicetree/bindings/phy | |
| parent | 8833ebf4f8530834ff8f95f309145f5e2da02999 (diff) | |
dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate
Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed2ca70..0d34b2b4a6b7 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port. |