diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-27 13:32:18 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-06-24 10:00:28 +0800 |
| commit | eade3750bf840948b29db26f0beabf10dea5f981 (patch) | |
| tree | ef0781c9c6d7f542203e55fb1ab4eec2cab67e2c /Documentation/devicetree/bindings/phy | |
| parent | 1bda33273eccae3c0d878d34660eca9da1765db0 (diff) | |
MLK-24171-2 dt-binding: phy: update the clock modes of pcie phy
Update the clock modes of iMX8MP PCIe PHY in binding DOC.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt index 627b508ecadc..77841c4959b0 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -6,6 +6,8 @@ Required properties: - reg: The base address and length of the registers - clocks: Phandles to the clocks for each clock listed in clock-names - clock-names: Must contain "phy" +- ext_osc: Specify the reference clock source. 1: external oscilltor is + used as PCIe reference clock. 0: internal PLL is used. - power-domains: Phandle to the power domain that the device is part of Example: |