diff options
| author | Lars Povlsen <lars.povlsen@microchip.com> | 2020-10-06 22:03:14 +0200 |
|---|---|---|
| committer | Sebastian Reichel <sre@kernel.org> | 2020-10-08 23:23:51 +0200 |
| commit | 312e95c6e92122fac0251a84efa1cf3914c877a6 (patch) | |
| tree | 8df2a320cf9e109b2dc49243f19d94033980cba3 /Documentation/devicetree/bindings/power/reset | |
| parent | 8ae237ec0af9f754c1da00913646f3c46a99a1cb (diff) | |
dt-bindings: reset: ocelot: Add Sparx5 support
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Diffstat (limited to 'Documentation/devicetree/bindings/power/reset')
| -rw-r--r-- | Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb3473..4d530d815484 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { |