diff options
author | Lee Jones <lee.jones@linaro.org> | 2014-07-14 15:33:28 +0100 |
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committer | Thierry Reding <thierry.reding@gmail.com> | 2014-08-07 16:19:40 +0200 |
commit | acad00d3d67ef2a7177beb70e7aeef5f0bd2bcf0 (patch) | |
tree | 68149a14e77b0a4e73714bef2e7353581f5ef2c9 /Documentation/devicetree/bindings/pwm | |
parent | 378fe115d19d6ab9e9210a2ac330159afabf0237 (diff) |
pwm: sti: Supply Device Tree binding documentation for ST's PWM IP
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pwm')
-rw-r--r-- | Documentation/devicetree/bindings/pwm/pwm-st.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/pwm-st.txt b/Documentation/devicetree/bindings/pwm/pwm-st.txt new file mode 100644 index 000000000000..84d2fb807d3c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-st.txt @@ -0,0 +1,41 @@ +STMicroelectronics PWM driver bindings +-------------------------------------- + +Required parameters: +- compatible : "st,pwm" +- #pwm-cells : Number of cells used to specify a PWM. First cell + specifies the per-chip index of the PWM to use and the + second cell is the period in nanoseconds - fixed to 2 + for STiH41x. +- reg : Physical base address and length of the controller's + registers. +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes + for PWM module. + For Pinctrl properties, please refer to [1]. +- clock-names: Set to "pwm". +- clocks: phandle of the clock used by the PWM module. + For Clk properties, please refer to [2]. + +Optional properties: +- st,pwm-num-chan: Number of available channels. If not passed, the driver + will consider single channel by default. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +[2] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Example: + +pwm1: pwm@fe510000 { + compatible = "st,pwm"; + reg = <0xfe510000 0x68>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clocks = <&clk_sysin>; + clock-names = "pwm"; + st,pwm-num-chan = <4>; +}; |