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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-14 15:31:58 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-14 15:31:58 -0700 |
commit | f888bdf9823c85fe945c4eb3ba353f749dec3856 (patch) | |
tree | 3bc21281538eb4f138d6aa280a4f44743b4b9d01 /Documentation/devicetree/bindings/pwm | |
parent | b4e1bce85fd8f43dc814049e2641cc6beaa8146b (diff) | |
parent | bd36e51d10e7c2b7d39ffa7d075aed98a8e7473c (diff) |
Merge tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Update dtc to upstream version v1.6.0-31-gcbca977ea121
- dtx_diff help text reformatting
- Speed-up validation time for binding and dtb checks using json for
intermediate files
- Add support for running yamllint on DT schema files
- Remove old booting-without-of.rst
- Extend the example schema to address common issues
- Cleanup handling of additionalProperties/unevaluatedProperties
- Ensure all DSI controller schemas reference dsi-controller.yaml
- Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex,
DFI, and Cisco Meraki
- Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
schema
- Convert HiSilicon SoC and syscon bindings to DT schema
- Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema
- Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR, SATA, vf610
GPIO, and UART to DT schema
- Add i.MX 8M compatible strings
- Add LM81 and DS1780 as trivial devices
- Various missing properties added to fix dtb validation warnings
* tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (111 commits)
dt-bindings: misc: explicitly add #address-cells for slave mode
spi: dt-bindings: spi-controller: explicitly require #address-cells=<0> for slave mode
dt: Remove booting-without-of.rst
dt-bindings: update usb-c-connector example
dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml
dt-bindings: arm: hisilicon: add missing properties into sysctrl.yaml
dt-bindings: pwm: imx: document i.MX compatibles
scripts/dtc: Update to upstream version v1.6.0-31-gcbca977ea121
dt-bindings: Add running yamllint to dt_binding_check
dt-bindings: powerpc: Add a schema for the 'sleep' property
dt-bindings: pinctrl: sirf: Fix typo abitrary
dt-bindings: pinctrl: qcom: Fix typo abitrary
dt-bindings: Explicitly allow additional properties in common schemas
dt-bindings: Use 'additionalProperties' instead of 'unevaluatedProperties'
dt-bindings: Add missing 'unevaluatedProperties'
Docs: Fixing spelling errors in Documentation/devicetree/bindings/
dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema
dt-bindings: riscv: convert pwm bindings to json-schema
dt-bindings: riscv: convert plic bindings to json-schema
dt-bindings: fu540: prci: convert PRCI bindings to json-schema
...
Diffstat (limited to 'Documentation/devicetree/bindings/pwm')
4 files changed, 93 insertions, 36 deletions
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml index 01df06777cba..379d693889f6 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml @@ -19,9 +19,28 @@ properties: - 3 compatible: - enum: - - fsl,imx1-pwm - - fsl,imx27-pwm + oneOf: + - enum: + - fsl,imx1-pwm + - fsl,imx27-pwm + - items: + - enum: + - fsl,imx25-pwm + - fsl,imx31-pwm + - fsl,imx50-pwm + - fsl,imx51-pwm + - fsl,imx53-pwm + - fsl,imx6q-pwm + - fsl,imx6sl-pwm + - fsl,imx6sll-pwm + - fsl,imx6sx-pwm + - fsl,imx6ul-pwm + - fsl,imx7d-pwm + - fsl,imx8mm-pwm + - fsl,imx8mn-pwm + - fsl,imx8mp-pwm + - fsl,imx8mq-pwm + - const: fsl,imx27-pwm reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt deleted file mode 100644 index 3d1dd7b06efc..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt +++ /dev/null @@ -1,33 +0,0 @@ -SiFive PWM controller - -Unlike most other PWM controllers, the SiFive PWM controller currently only -supports one period for all channels in the PWM. All PWMs need to run at -the same period. The period also has significant restrictions on the values -it can achieve, which the driver rounds to the nearest achievable period. -PWM RTL that corresponds to the IP block version numbers can be found -here: - -https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm - -Required properties: -- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". - Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive - PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the - SiFive PWM v0 IP block with no chip integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details. -- reg: physical base address and length of the controller's registers -- clocks: Should contain a clock identifier for the PWM's parent clock. -- #pwm-cells: Should be 3. See pwm.yaml in this directory - for a description of the cell format. -- interrupts: one interrupt per PWM channel - -Examples: - -pwm: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - clocks = <&tlclk>; - interrupt-parent = <&plic>; - interrupts = <42 43 44 45>; - #pwm-cells = <3>; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml new file mode 100644 index 000000000000..5ac25275d8bf --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive PWM controller + +maintainers: + - Yash Shah <yash.shah@sifive.com> + - Sagar Kadam <sagar.kadam@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + Unlike most other PWM controllers, the SiFive PWM controller currently + only supports one period for all channels in the PWM. All PWMs need to + run at the same period. The period also has significant restrictions on + the values it can achieve, which the driver rounds to the nearest + achievable period. PWM RTL that corresponds to the IP block version + numbers can be found here - + + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm + +properties: + compatible: + items: + - const: sifive,fu540-c000-pwm + - const: sifive,pwm0 + description: + Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported + compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 + as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the + SiFive PWM v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + + interrupts: + maxItems: 4 + description: + Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator. + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + - interrupts + +additionalProperties: false + +examples: + - | + pwm: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x10020000 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42>, <43>, <44>, <45>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml index fa4f9de92090..7d1f687cee9c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm.yaml @@ -20,6 +20,8 @@ properties: required: - "#pwm-cells" +additionalProperties: true + examples: - | pwm: pwm@7000a000 { |