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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2021-07-08 09:59:49 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-08-04 08:49:58 -0700 |
| commit | ecd4916c7261edccb2382c9931535e238875a44d (patch) | |
| tree | 4f02b4c09c0b6bd75dcf5b8dfc0bb3fb72815ebc /Documentation/devicetree/bindings/riscv | |
| parent | bcf11b5e99b27472ea61231a64e29ad7dd31f0da (diff) | |
riscv: Enable GENERIC_IRQ_SHOW_LEVEL
The interrupt controllers on riscv support both edge and level triggered
interrupts, it's useful to provide that information in /proc/interrupts.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
0 files changed, 0 insertions, 0 deletions