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authorKrishna Yarlagadda <kyarlagadda@nvidia.com>2019-09-04 10:13:00 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-09-05 10:00:04 +0200
commitc9fd37f926fc57c2788504da429521227ab5a024 (patch)
tree78999134c6e2102de5ef4fce1e40c5b9daaddf5f /Documentation/devicetree/bindings/serial
parentcb79f504bb261460bd54b8a5577100f21982b20a (diff)
dt-binding: serial: tegra: add new chips
Add new compatible string for Tegra186. It differs from earlier chips as it has FIFO mode enable check and 8 byte DMA buffer. Add new compatible string for Tegra194. Tegra194 has different error tolerance levels for baud rate compared to older chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/1567572187-29820-6-git-send-email-kyarlagadda@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial')
-rw-r--r--Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index d7edf732eb7f..dab31d44c4cd 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -1,7 +1,12 @@
NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
Required properties:
-- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+- compatible : should be,
+ "nvidia,tegra20-hsuart" for Tegra20,
+ "nvidia,tegra30-hsuart" for Tegra30,
+ "nvidia,tegra186-hsuart" for Tegra186,
+ "nvidia,tegra194-hsuart" for Tegra194.
+
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain one entry, for the module clock.