diff options
| author | Shunli Wang <shunli.wang@mediatek.com> | 2019-01-22 14:39:09 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-01-25 18:07:04 +0000 |
| commit | bfd74e65c47ff325924fe5bd90789b1db422c9cc (patch) | |
| tree | 6a1644895b86f1b23e45a536b87c4bc82f3a4758 /Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt | |
| parent | a94aec035a122bf6d1a05b14f02f34c34b99506a (diff) | |
ASoC: mediatek: mt8183: add audio afe document
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt new file mode 100644 index 000000000000..396ba38619f6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt @@ -0,0 +1,36 @@ +Mediatek AFE PCM controller for mt8183 + +Required properties: +- compatible = "mediatek,mt68183-audio"; +- reg: register location and size +- interrupts: should contain AFE interrupt +- power-domains: should define the power domain +- clocks: Must contain an entry for each entry in clock-names +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_sys_pll3_d4", + "top_clk26m_clk"; + +Example: + + afe: mt8183-afe-pcm@11220000 { + compatible = "mediatek,mt8183-audio"; + reg = <0 0x11220000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&infrasys CLK_INFRA_AUDIO>, + <&infrasys CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&clk26m>; + clock-names = "infra_sys_audio_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_sys_pll_d2_d4", + "top_clk26m_clk"; + }; |