diff options
| author | Masanari Iida <standby24x7@gmail.com> | 2016-06-29 04:33:33 +0900 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-06-28 20:35:48 +0100 |
| commit | 0fb7620fba7feb977a5138f8d7f6b42514f81ea9 (patch) | |
| tree | 12564fb64c22988ad8976f6cfdcfaf80e65afea4 /Documentation/devicetree/bindings/spi | |
| parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
spi: Fix typo in devicetree/bindings/spi
This patch fix spelling typos found in
Documentation/devicetree/bingings/spi.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-davinci.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/spi/ti_qspi.txt | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt index d1e914adcf6e..f5916c92fe91 100644 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -21,7 +21,7 @@ Required properties: IP to the interrupt controller within the SoC. Possible values are 0 and 1. Manual says one of the two possible interrupt lines can be tied to the interrupt controller. Set this - based on a specifc SoC configuration. + based on a specific SoC configuration. - interrupts: interrupt number mapped to CPU. - clocks: spi clk phandle diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt index 50b14f6b53a3..e65fde4a7388 100644 --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt @@ -20,7 +20,7 @@ Optional properties: chipselect register and offset of that register. NOTE: TI QSPI controller requires different pinmux and IODelay -paramaters for Mode-0 and Mode-3 operations, which needs to be set up by +parameters for Mode-0 and Mode-3 operations, which needs to be set up by the bootloader (U-Boot). Default configuration only supports Mode-0 operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be specified in the slave nodes of TI QSPI controller without appropriate |