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authorVignesh R <vigneshr@ti.com>2016-04-20 17:03:00 +0530
committerTony Lindgren <tony@atomide.com>2016-04-26 10:52:19 -0700
commitb7a1922814c617884a3fee9b107ffb784fa4cf94 (patch)
treed5fb949550369dcef0c791d4c3e89a4bb2cd20dc /Documentation/devicetree/bindings/spi
parent626180785f5d9443c475d2b2760f64bb510f2b66 (diff)
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/ti_qspi.txt7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index cc8304aa64ac..50b14f6b53a3 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -19,6 +19,13 @@ Optional properties:
- syscon-chipselects: Handle to system control region contains QSPI
chipselect register and offset of that register.
+NOTE: TI QSPI controller requires different pinmux and IODelay
+paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
+the bootloader (U-Boot). Default configuration only supports Mode-0
+operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
+specified in the slave nodes of TI QSPI controller without appropriate
+modification to bootloader.
+
Example:
For am4372: