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authorDong Aisheng <aisheng.dong@nxp.com>2017-08-01 16:40:16 +0800
committerDaniel Lezcano <daniel.lezcano@linaro.org>2017-08-29 11:07:55 +0200
commit34b0c26cd5458a991626bc8424e029562dceed21 (patch)
treebab74eb80f80e83fdffbd5e9c82144f1b13569b3 /Documentation/devicetree/bindings/timer
parent4e2a809703e2b2300438a425b0a3f2013b55fcc6 (diff)
dt-bindings: timer: Add nxp tpm timer binding doc
Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM) binding doc. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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+NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+The Timer/PWM Module (TPM) supports input capture, output compare,
+and the generation of PWM signals to control electric motor and power
+management applications. The counter, compare and capture registers
+are clocked by an asynchronous clock that can remain enabled in low
+power modes. TPM can support global counter bus where one TPM drives
+the counter bus for the others, provided bit width is the same.
+
+Required properties:
+
+- compatible : should be "fsl,imx7ulp-tpm"
+- reg : Specifies base physical address and size of the register sets
+ for the clock event device and clock source device.
+- interrupts : Should be the clock event device interrupt.
+- clocks : The clocks provided by the SoC to drive the timer, must contain
+ an entry for each entry in clock-names.
+- clock-names : Must include the following entries: "igp" and "per".
+
+Example:
+tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+};