diff options
author | Ran Wang <ran.wang_1@nxp.com> | 2019-01-16 12:43:38 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:57:07 +0800 |
commit | bca3c354c873d0c925c27e384e4758adf1ab2f05 (patch) | |
tree | 8216f51e19dc073f379d12b7c348640d2c403d4d /Documentation/devicetree/bindings/usb | |
parent | 7241ae6d919d8000e3b534737847b7cfd6d17add (diff) |
usb: dwc3: Add avoiding vbus glitch happen during xhci reset
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will turn on immediately on related Root Hub
ports. Then the VBUS will be de-asserted for a little while during xhci
reset (conducted by xhci driver) for a little while and back to normal.
This VBUS glitch might cause some USB devices emuration fail if kernel
boot with them connected. One SW workaround which can fix this is to
program all PORTSC[PP] to 0 to turn off VBUS immediately after setting
host mode in DWC3 driver(per signal measurement result, it will be too
late to do it in xhci-plat.c or xhci.c).
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/usb')
-rw-r--r-- | Documentation/devicetree/bindings/usb/dwc3.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 66780a47ad85..d2d5a8e99db5 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -109,6 +109,10 @@ Optional properties: more than one value, which means undefined length INCR burst type enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. + - snps,host-vbus-glitches: Power off all Root Hub ports immediately after + setting host mode to avoid vbus (negative) glitch happen in later + xhci reset. And the vbus will back to 5V automatically when reset done. + - in addition all properties from usb-xhci.txt from the current directory are supported as well |