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| author | Liu Ying <victor.liu@nxp.com> | 2019-07-17 15:08:07 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:45:15 +0800 |
| commit | 9ff00c698af673767085a8452ec1304fea6d707b (patch) | |
| tree | 6c311d5d73e708095275f8f0339f53020614f7b6 /Documentation/devicetree/bindings/vendor-prefixes.yaml | |
| parent | 2738e0707ca871212b19dbb1656ae19cd8432dc5 (diff) | |
phy: mixel-lvds-combo: Configure CO divider to meet fvco range requirement
As the below diagram shows, to achieve a particular serial clock rate,
we should choose an appropriate CO divider value(1/2/4/8) so that PLL
VCO frequency(fvco) is in specified range(640MHz ~ 1500MHz).
--------- 640MHz ~ 1500MHz ------------ --------------
| PLL VCO | ----------------> | CO divider | -> | serial clock |
--------- ------------ --------------
1/2/4/8 div 7 * phy_clk_rate
This patch configures CO divider to be appropriate value to meet the fvco
range requirement. This may address display flicker issue seen on some
SoC samples.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree/bindings/vendor-prefixes.yaml')
0 files changed, 0 insertions, 0 deletions