diff options
author | Bhupesh Sharma <bhupesh.sharma@freescale.com> | 2015-12-28 15:31:23 +0530 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2015-12-31 16:40:00 +0100 |
commit | 766faef1f4c0b37b2cb2c0de214dacf54e29ac05 (patch) | |
tree | 50261f6e62504c5bf0a85068d6a0a80944ae4c89 /Documentation/devicetree/bindings/watchdog | |
parent | 0ac01488315bac92de1b2086d87607b7ef798e8c (diff) |
Documentation: DT: Add entry for ARM SP805-WDT
This patch adds a devicetree binding documentation for ARM's
SP805 WatchDog Timer.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/watchdog')
-rw-r--r-- | Documentation/devicetree/bindings/watchdog/sp805-wdt.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file mode 100644 index 000000000000..edc4f0ea54a3 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt @@ -0,0 +1,31 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- clocks : From common clock binding. + First clock is PCLK and the second is WDOGCLK. + WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency. +- clock-names : From common clock binding. + Shall be "apb_pclk" for first clock and "wdog_clk" for the + second one. + +Optional properties: +- interrupts : Should specify WDT interrupt number. + +Examples: + + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + |