arm: tegra: tn8-ers: dt: enable support for emc tables

Rearrange parsing of dt nodes of emc tables
Add emc dvfs tables for tn8 ers

Bug 1360455

Change-Id: I21a81a67d315bba9dd7af792ddaebe251dc505cd
Signed-off-by: Ryane Luo <ryanel@nvidia.com>
Reviewed-on: http://git-master/r/299848
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>

1 files changed, 132 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
index fb795bfaee2f..18967ccf0aa7 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
@@ -265,3 +265,135 @@ optional properties:
 			nvidia,emc-mode-4 = <0>;
 			nvidia,emc-min-mv = <0>;
 		};
+
+Tables for Tegra124:
+
+Properties:
+- name : Should be emc-table
+- compatible : Should contain "nvidia,tegra12-emc-table".
+- reg : either an opaque enumerator to tell different tables apart, or
+  the valid frequency for which the table should be used (in kHz).
+- nvidia,revision : SDRAM revision.
+- nvidia,dvfs-version : DVFS table versionl.
+- clock-frequency : the clock frequency for the EMC at which this
+  table should be used (in kHz).
+- nvidia,emc-min-mv : Minimum voltage
+- nvidia,source : Source name.
+- nvidia,src-sel-reg : Source register settings.
+- nvidia, burst-regs-num : Number of emc-registers.
+- nvidia,burst-up-down-regs-num : Number of up_down_regs.
+- nvidia,emc-registers : a word array of EMC registers to be programmed.
+  for operation at the 'clock-frequency' setting.
+  The order and contents of the registers are:
+    RC, RFC, RFC_SLR, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD,
+    RRD, REXT, WEXT, WDV, WDV_MASK, QUSE, QUSE_WIDTH, IBDLY, EINPUT,
+    EINPUT_DURATION, PUTERM_EXTRA, PUTERM_WIDTH, PUTERM_ADJ, CDB_CNTL_1,
+    CDB_CNTL_2, CDB_CNTL_3, QRST, QSAFE, RDV, RDV_MASK, REFRESH,
+    BURST_REFRESH_NUM, PRE_REFRESH_REQ_CNT, PDEX2WR, PDEX2RD, PCHG2PDEN,
+    ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TXSRDLL, TCKE, TCKESR, TPD, TFAW,
+    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, FBIO_CFG6, ODT_WRITE, ODT_READ,
+    FBIO_CFG5, CFG_DIG_DLL, CFG_DIG_DLL_PERIOD, DLL_XFORM_DQS0,
+    DLL_XFORM_DQS1, DLL_XFORM_DQS2, DLL_XFORM_DQS3, DLL_XFORM_DQS4,
+    DLL_XFORM_DQS5, DLL_XFORM_DQS6, DLL_XFORM_DQS7, DLL_XFORM_DQS8,
+    DLL_XFORM_DQS9, DLL_XFORM_DQS10, DLL_XFORM_DQS11, DLL_XFORM_DQS12,
+    DLL_XFORM_DQS13, DLL_XFORM_DQS14, DLL_XFORM_DQS15, DLL_XFORM_QUSE0,
+    DLL_XFORM_QUSE1, DLL_XFORM_QUSE2, DLL_XFORM_QUSE3, DLL_XFORM_QUSE4,
+    DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, DLL_XFORM_QUSE7, DLL_XFORM_ADDR0,
+    DLL_XFORM_ADDR1, DLL_XFORM_ADDR2, DLL_XFORM_ADDR3, DLL_XFORM_ADDR4,
+    DLL_XFORM_ADDR5, DLL_XFORM_QUSE8, DLL_XFORM_QUSE9, DLL_XFORM_QUSE10,
+    DLL_XFORM_QUSE11, DLL_XFORM_QUSE12, DLL_XFORM_QUSE13, DLL_XFORM_QUSE14,
+    DLL_XFORM_QUSE15, DLI_TRIM_TXDQS0, DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2,
+    DLI_TRIM_TXDQS3, DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6,
+    DLI_TRIM_TXDQS7, DLI_TRIM_TXDQS8, DLI_TRIM_TXDQS9, DLI_TRIM_TXDQS10,
+    DLI_TRIM_TXDQS11, DLI_TRIM_TXDQS12, DLI_TRIM_TXDQS13, DLI_TRIM_TXDQS14,
+    DLI_TRIM_TXDQS15, DLL_XFORM_DQ0, DLL_XFORM_DQ1, DLL_XFORM_DQ2,
+    DLL_XFORM_DQ3, DLL_XFORM_DQ4, DLL_XFORM_DQ5, DLL_XFORM_DQ6,
+    DLL_XFORM_DQ7, XM2CMDPADCTRL, XM2CMDPADCTRL4, XM2CMDPADCTRL5,
+    XM2DQSPADCTRL2, XM2DQPADCTRL2, XM2DQPADCTRL3, XM2CLKPADCTRL,
+    XM2CLKPADCTRL2, XM2COMPPADCTRL, XM2VTTGENPADCTRL, XM2VTTGENPADCTRL2,
+    XM2VTTGENPADCTRL3, XM2DQSPADCTRL3, XM2DQSPADCTRL4, XM2DQSPADCTRL5,
+    XM2DQSPADCTRL6, DSR_VTTGEN_DRV, TXDSRVTTGEN, FBIO_SPARE, ZCAL_INTERVAL,
+    ZCAL_WAIT_CNT, MRS_WAIT_CNT, MRS_WAIT_CNT2, AUTO_CAL_CONFIG2,
+    AUTO_CAL_CONFIG3, AUTO_CAL_CONFIG, CTT, CTT_DURATION, CFG_PIPE,
+    DYN_SELF_REF_CONTROL, QPOP, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ,
+    EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC,
+    EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD,
+    EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R,
+    EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R,
+    EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0,
+    EMEM_ARB_RING1_THROTTLE
+
+- nvidia, burst-up-down-regs : a word array of burst register values
+  The order and contents of the registers are:
+    MLL_MPCORER_PTSA_RATE, PTSA_GRANT_DECREMENT, LATENCY_ALLOWANCE_XUSB_0,
+    LATENCY_ALLOWANCE_XUSB_1, LATENCY_ALLOWANCE_TSEC_0,
+    LATENCY_ALLOWANCE_SDMMCA_0,LATENCY_ALLOWANCE_SDMMCAA_0,
+    LATENCY_ALLOWANCE_SDMMC_0, LATENCY_ALLOWANCE_SDMMCAB_0,
+    LATENCY_ALLOWANCE_PPCS_0, LATENCY_ALLOWANCE_PPCS_1,
+    LATENCY_ALLOWANCE_MPCORE_0, LATENCY_ALLOWANCE_MPCORELP_0,
+    LATENCY_ALLOWANCE_HC_0, LATENCY_ALLOWANCE_HC_1,
+    LATENCY_ALLOWANCE_AVPC_0, LATENCY_ALLOWANCE_GPU_0,
+    LATENCY_ALLOWANCE_MSENC_0, LATENCY_ALLOWANCE_HDA_0,
+    LATENCY_ALLOWANCE_VIC_0, LATENCY_ALLOWANCE_VI2_0,
+    LATENCY_ALLOWANCE_ISP2_0, LATENCY_ALLOWANCE_ISP2_1,
+    LATENCY_ALLOWANCE_ISP2B_0, LATENCY_ALLOWANCE_ISP2B_1,
+    LATENCY_ALLOWANCE_VDE_0, LATENCY_ALLOWANCE_VDE_1,
+    LATENCY_ALLOWANCE_VDE_2, LATENCY_ALLOWANCE_VDE_3,
+    LATENCY_ALLOWANCE_SATA_0, LATENCY_ALLOWANCE_AFI_0
+
+- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
+- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL
+- nvidia,emc-ctt-term_ctrl : Configure CTT termination output drive strength
+- nvidia,emc-cfg : Configuration Register
+- nvidia,emc-cfg-2 : EMC Configuration 2
+- nvidia,emc-sel-dpd-ctrl : Configures functional SEL_DPD modes
+- nvidia,emc-cfg-dig-dll : Configure Digital DLL.
+- nvidia,emc-mode-0 : Mode Register 0
+- nvidia,emc-mode-1 : Mode Register 1
+- nvidia,emc-mode-2 : Mode Register 2
+- nvidia,emc-mode-4 : Mode Register 4
+
+optional properties:
+- nvidia,gk20a-min-mv : gpu min voltage
+
+	emc-table@40800 {
+		compatible = "nvidia,tegra12-emc-table";
+		nvidia,revision = <0>;
+		nvidia,dvfs-version = "04_40800_0_V5.0.1_V0.3";
+		clock-frequency = <40800>;
+		nvidia,emc-min-mv = <0>;
+		nvidia,gk20a-min-mv = <800>;
+		nvidia,source = "pllp_out0";
+		nvidia,src-sel-reg = <0>;
+		nvidia,burst-regs-num = <167>;
+		nvidia,burst-up-down-regs-num = <31>;
+		nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0>;
+		nvidia,emc-burst-up-down-regs = <
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0 0 0 0 0 0 0 0 0 0 0 0
+			0 0 0>;
+		nvidia,emc-zcal-cnt-long = <0>;
+		nvidia,emc-acal-interval = <0>;
+		nvidia,emc-ctt-term_ctrl = <0>;
+		nvidia,emc-cfg = <0>;
+		nvidia,emc-cfg-2 = <0>;
+		nvidia,emc-sel-dpd-ctrl = <0>;
+		nvidia,emc-cfg-dig-dll = <0>;
+		nvidia,emc-mode-0 = <0>;
+		nvidia,emc-mode-1 = <0>;
+		nvidia,emc-mode-2 = <0>;
+		nvidia,emc-mode-4 = <0>;
+	};