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authorLinus Torvalds <torvalds@linux-foundation.org>2015-06-23 17:27:09 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2015-06-23 17:27:09 -0700
commit5a602e157a9d91d5ce98d07c404097edba8ec9f3 (patch)
tree9ad220ea4638fc7d99c3303cc80c0066d1ea3999 /Documentation/devicetree
parente12bdf0d9265a90664a4767f4ffc20af06807278 (diff)
parentfda052b0a52261ecad8c8beb6bcfa1663a35975f (diff)
Merge tag 'spi-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "No framework updates for the SPI API this time around aside from one small fix, just driver improvments. Some highlights include: - New driver support for CSR USP, Mikrotik RB4xx and Zynq GQSPI controllers. - Modernisation of the OMAP McSPI controller driver, moving it to current APIs to enable support for a wider range of client drivers. - DMA support for the bcm2835 controller" * tag 'spi-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (60 commits) spi: zynq: Remove execute bit spi: atmel: add support to FIFOs spi: atmel: update DT bindings documentation spi: spi-fsl-dspi: Update DT binding documentation spi: pxa2xx: Constify ACPI device ids spi: Add support for Zynq Ultrascale+ MPSoC GQSPI controller spi: zynq: Add DT bindings documentation for Zynq Ultrascale+ MPSoC GQSPI controller spi: fsl-dspi: Use pinctrl PM helpers spi: davinci: change the lower limit of pre-scale divider to 1 spi: spi-fsl-dspi: Change the way of increasing spi_message->actual_length spi: spi-fsl-dspi: Enable TCF interrupt mode support spi: atmel: add support for the internal chip-select of the spi controller spi: spi-pxa2xx: remove legacy PXA DMA bits spi: pxa2xx: Make LPSS SPI general register optional spi: pxa2xx: Prepare for new Intel LPSS SPI type spi: pxa2xx: Differentiate Intel LPSS types spi: restore rx/tx_buf in case of unset CONFIG_HAS_DMA spi: rspi: Re-do the returning value of qspi_transfer_out_in spi: rspi: modify the name of "qspi_trigger_transfer_out_int" function spi: orion: Fix extended baud rates for each Armada SoCs ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/spi/spi-ath79.txt24
-rw-r--r--Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt2
-rw-r--r--Documentation/devicetree/bindings/spi/spi-orion.txt8
-rw-r--r--Documentation/devicetree/bindings/spi/spi-sirf.txt3
-rw-r--r--Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt26
-rw-r--r--Documentation/devicetree/bindings/spi/spi_atmel.txt8
-rw-r--r--Documentation/devicetree/bindings/spi/spi_pl022.txt2
7 files changed, 68 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt
new file mode 100644
index 000000000000..f1ad9c367532
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-ath79.txt
@@ -0,0 +1,24 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- clocks: phandle to the AHB clock.
+- clock-names: has to be "ahb".
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@1F000000 {
+ compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+ reg = <0x1F000000 0x10>;
+
+ clocks = <&pll 2>;
+ clock-names = "ahb";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index 70af78a9185e..fa77f874e321 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -1,7 +1,7 @@
ARM Freescale DSPI controller
Required properties:
-- compatible : "fsl,vf610-dspi"
+- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- clocks: from common clock binding: handle to dspi clock.
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt
index 50c3a3de61c1..98bc69815eb3 100644
--- a/Documentation/devicetree/bindings/spi/spi-orion.txt
+++ b/Documentation/devicetree/bindings/spi/spi-orion.txt
@@ -1,7 +1,13 @@
Marvell Orion SPI device
Required properties:
-- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi".
+- compatible : should be on of the following:
+ - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
+ - "marvell,armada-370-spi", for the Armada 370 SoCs
+ - "marvell,armada-375-spi", for the Armada 375 SoCs
+ - "marvell,armada-380-spi", for the Armada 38x SoCs
+ - "marvell,armada-390-spi", for the Armada 39x SoCs
+ - "marvell,armada-xp-spi", for the Armada XP SoCs
- reg : offset and length of the register set for the device
- cell-index : Which of multiple SPI controllers is this.
Optional properties:
diff --git a/Documentation/devicetree/bindings/spi/spi-sirf.txt b/Documentation/devicetree/bindings/spi/spi-sirf.txt
index 4c7adb8f777c..ddd78ff68fae 100644
--- a/Documentation/devicetree/bindings/spi/spi-sirf.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sirf.txt
@@ -1,7 +1,8 @@
* CSR SiRFprimaII Serial Peripheral Interface
Required properties:
-- compatible : Should be "sirf,prima2-spi"
+- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp"
+ or "sirf,atlas7-usp"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI interrupt
- resets: phandle to the reset controller asserting this device in
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
new file mode 100644
index 000000000000..c8f50e5cf70b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
@@ -0,0 +1,26 @@
+Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
+-------------------------------------------------------------------
+
+Required properties:
+- compatible : Should be "xlnx,zynqmp-qspi-1.0".
+- reg : Physical base address and size of GQSPI registers map.
+- interrupts : Property with a value describing the interrupt
+ number.
+- interrupt-parent : Must be core interrupt controller.
+- clock-names : List of input clock names - "ref_clk", "pclk"
+ (See clock bindings for details).
+- clocks : Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs : Number of chip selects used.
+
+Example:
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ interrupts = <0 15 4>;
+ interrupt-parent = <&gic>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index 4f8184d069cb..fb588b3e6a9a 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -4,11 +4,16 @@ Required properties:
- compatible : should be "atmel,at91rm9200-spi".
- reg: Address and length of the register set for the device
- interrupts: Should contain spi interrupt
-- cs-gpios: chipselects
+- cs-gpios: chipselects (optional for SPI controller version >= 2 with the
+ Chip Select Active After Transfer feature).
- clock-names: tuple listing input clock names.
Required elements: "spi_clk"
- clocks: phandles to input clocks.
+Optional properties:
+- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
+ capable SPI controllers.
+
Example:
spi1: spi@fffcc000 {
@@ -20,6 +25,7 @@ spi1: spi@fffcc000 {
clocks = <&spi1_clk>;
clock-names = "spi_clk";
cs-gpios = <&pioB 3 0>;
+ atmel,fifo-size = <32>;
status = "okay";
mmc-slot@0 {
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
index 22ed6797216d..4d1673ca8cf8 100644
--- a/Documentation/devicetree/bindings/spi/spi_pl022.txt
+++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt
@@ -4,9 +4,9 @@ Required properties:
- compatible : "arm,pl022", "arm,primecell"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
+- num-cs : total number of chipselects
Optional properties:
-- num-cs : total number of chipselects
- cs-gpios : should specify GPIOs used for chipselects.
The gpios will be referred to as reg = <index> in the SPI child nodes.
If unspecified, a single SPI device without a chip select can be used.