MLK-16347-4: drm/imx: Add mipi-dsi driver for mx8

Add support for the NorthWest Logic MIPI-DSI controller found
in the following i.MX8 platforms: i.MX8qm, i.MX8qxp and i.MX8mq.
This is the MIPI-DSI encoder containing the platform specific changes
and it uses the NWL MIPI-DSI bridge.
Currently only qm and qxp are tested with this driver. The mq support
will be added later.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

1 files changed, 120 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt b/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt
new file mode 100644
index 000000000000..6ff608f3320d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt
@@ -0,0 +1,120 @@
+NXP specific extensions to the Northwest Logic MIPI-DSI
+================================
+
+Platform specific extentions for the NWL MIPI-DSI host controller found in
+MX8 platforms.
+
+Required properties:
+- compatible: 		"fsl,<chip>-mipi-dsi"
+	The following strings are expected:
+			"fsl,imx8qm-mipi-dsi"
+			"fsl,imx8qxp-mipi-dsi"
+- reg: 			the register range of the MIPI-DSI controller
+- interrupts: 		the interrupt number for this module
+- clock, clock-names: 	phandles to the MIPI-DSI clocks
+	The following clocks are expected on all platforms:
+		"phy_ref" - PHY_REF clock
+		"tx_esc"  - TX_ESC clock (used in escape mode)
+		"rx_esc"  - RX_ESC clock (used in escape mode)
+	The following clocks are expected on i.MX8qm and i.MX8qxp:
+		"bypass"  - bypass clock
+		"pixel"   - pixel clock (for the pixel link)
+- assigned-clocks:	phandles to clocks that requires initial configuration
+- assigned-clock-rates:	rates of the clocks that requires initial configuration
+	The following clocks needs to have an initial configuration:
+	"tx_esc" and "rx_esc"
+- port: 		input and output port nodes with endpoint definitions as
+			defined in Documentation/devicetree/bindings/graph.txt;
+			the input port should be connected to a display
+			interface and the output port should be connected to a
+			panel or a bridge input port
+- phys: 		phandle to the phy module representing the DPHY
+			inside MIPI-DSI IP block
+- phy-names: 		should be "dphy"
+
+Optional properties:
+- power-domains 	phandle to the power domain
+- interrupt-parent 	phandle to the interrupt parent, if there is one;
+			usually, on i.MX8qm and i.MX8qxp there is an irq
+			steer handling the MIPI DSI interrupts
+- csr 			phandle to the CSR register set (required on i.MX8qm
+			and i.MX8qxp for the reset functions)
+- assigned-clock-parents phandles to parent clocks that needs to be assigned as
+			parents to clocks defined in assigned-clocks
+
+Example:
+	mipi_dsi1: mipi_dsi@56228000 {
+                compatible = "fsl,imx8qm-mipi-dsi";
+                reg = <0x0 0x56228000 0x0 0x1000>;
+                interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&irqsteer_dsi0>;
+                clocks =
+                        <&clk IMX8QM_MIPI0_PXL_CLK>,
+                        <&clk IMX8QM_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QM_CLK_DUMMY>,
+                        <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
+                        <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
+                clock-names = "pixel", "bypass", "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,
+                                  <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;
+		assigned-clock-rates = <18000000>, <72000000>;
+                power-domains = <&pd_mipi0>;
+                csr = <&mipi_dsi_csr1>;
+                phys = <&mipi_dsi_phy1>;
+                phy-names = "dphy";
+
+                port@0 {
+                        mipi_dsi1_in: endpoint {
+                                remote-endpoint = <&dpu1_disp0_mipi_dsi>;
+                        };
+                };
+
+		port@1 {
+                        mipi_dsi1_out: endpoint {
+                                remote-endpoint = <&adv7535_1_in>;
+                        };
+                };
+        };
+
+Another example, for a platform with a complex clock tree, like 8QXP:
+	mipi_dsi1: mipi_dsi@56228000 {
+		compatible = "fsl,imx8qxp-mipi-dsi";
+		reg = <0x0 0x56228000 0x0 0x300>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_mipi_lvds0>;
+		clocks =
+			<&clk IMX8QXP_MIPI0_PIXEL_CLK>,
+			<&clk IMX8QXP_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
+		clock-names = "pixel", "bypass", "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks =
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
+		assigned-clock-rates = <0>, <0>, <18000000>, <72000000>;
+		assigned-clock-parents =
+			<&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>;
+		power-domains = <&pd_mipi_dsi0>;
+		csr = <&mipi_dsi_csr1>;
+		phys = <&mipi_dsi_phy1>;
+		phy-names = "dphy";
+
+		port@0 {
+			mipi_dsi1_in: endpoint {
+				remote-endpoint = <&dpu_disp0_mipi_dsi>;
+			};
+		};
+
+		port@1 {
+                        mipi_dsi1_out: endpoint {
+                                remote-endpoint = <&adv7535_1_in>;
+                        };
+                };
+	};
+
+* Here, we set the clock parents for the *_SEL clocks (which are the sources of
+the *_CLK clocks) and also the clock rate of the *_CLK clocks.