diff options
| author | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2017-10-19 12:27:23 +0300 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 90eed9a4f9d2f3f43aa9a58fb25a297557f9db74 (patch) | |
| tree | 1058d2808273f3a836ae873c3e41fefe2cf109ac /Documentation/devicetree | |
| parent | a8f971c0d3de057361c763c2cd2eb8407f6580eb (diff) | |
MLK-16675-1: drm: imx: add mscale DCSS core driver
This patch adds base suport for i.MX8M's Display Controller
subsystem(DCSS). It has built-in DPR, Scaler and HDR10 modules. Also, it
features a video Decompression and Tile to Raster Conversion (DTRC) unit,
as well as a graphics pixel decompression infrastracture (DEC400D).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 8553f63f7a14..6a5c927ecbb6 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -124,6 +124,73 @@ dpu: dpu@56180000 { }; }; + +NXP i.MX Display Controller Subsystem (DCSS) +============================================= + +Required properties: +- compatible: Should be "nxp,<chip>-dcss" +- reg: should be register base and length as documented in the + datasheet. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- interrupt-parent: contains the phandle to IRQ Steer module. +- clocks, clock-names: phandles to the DCSS clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt +- disp-dev: can take following values: + - hdmi_disp: DCSS output goes to HDMI + - mipi_disp: DCSS output goes to MIPI_DSI +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + + +example: + +dcss_drm: dcss@0x32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x0 0x32e00000 0x0 0x30000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>, + <6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld", + "dtg_prg1"; + interrupt-parent = <&irqsteer_dcss>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", "pixel", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_APB_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_DTRC_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rate = <800000000>, <800000000>, <800000000>, <594000000>, <25000000>; + + disp-dev = "hdmi_disp"; + + status = "okay"; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_imx_stub: imx_stub_conenc { + remote-endpoint = <&imx_stub_conenc0>; + }; + }; +}; + + Parallel display support ======================== |