diff options
author | Liu Ying <victor.liu@nxp.com> | 2022-05-30 14:19:49 +0800 |
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committer | Liu Ying <victor.liu@nxp.com> | 2022-07-13 13:06:06 +0800 |
commit | b92769b4d678fb5e5f437bc5304b5d92ca50cd4b (patch) | |
tree | dd073d05caf78a7a5a247880043942e00aca7e31 /Documentation/devicetree | |
parent | 6213cecbe5111b9ed08915008d0b9169cb12a92c (diff) |
LF-2650-1 dt-bindings: phy: Add bindings for i.MX93 Synopsys DesignWare MIPI DPHY
This patch adds DT bindings for Freescale i.MX93
Synopsys DesignWare MIPI DPHY.
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml new file mode 100644 index 000000000000..222b4f9ef683 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx93-mipi-dphy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx93-mipi-dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX93 Synopsys DesignWare MIPI DPHY + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +properties: + compatible: + const: fsl,imx93-mipi-dphy + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY configuration clock + - description: PHY reference clock + + clock-names: + items: + - const: phy_cfg + - const: phy_ref + + power-domains: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx93-clock.h> + #include <dt-bindings/power/imx93-power.h> + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + }; + +... |