Merge branch 'dts/next' into next

* dts/next: (765 commits)
  arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
  arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
  arm64: dts: fsl: Drop "compatible" string from Felix switch
  arm64: dts: fsl: Specify phy-mode for CPU ports
  LF-261: arm64: dts: imx8mq: Set parent clock for IMX8MQ_CLK_AUDIO_AHB
  ...

7 files changed, 179 insertions, 15 deletions

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
index b5cb374dc47d..10a91cc8b997 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
@@ -8,7 +8,7 @@ Required properties:
   - compatible: Should contain a chip-specific compatible string,
 	Chip-specific strings are of the form "fsl,<chip>-dcfg",
 	The following <chip>s are known to be supported:
-	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
 
   - reg : should contain base address and length of DCFG memory-mapped registers
 
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 1b4b4e6573b5..415ceaf673b4 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -287,6 +287,7 @@ properties:
               - ebs-systart,oxalis
               - fsl,ls1012a-rdb
               - fsl,ls1012a-frdm
+              - fsl,ls1012a-frwy
               - fsl,ls1012a-qds
           - const: fsl,ls1012a
 
@@ -335,4 +336,11 @@ properties:
               - fsl,ls2088a-rdb
           - const: fsl,ls2088a
 
+      - description: LX2160A based Boards
+        items:
+          - enum:
+              - fsl,lx2160a-qds
+              - fsl,lx2160a-rdb
+          - const: fsl,lx2160a 
+
 ...
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index f7d48f23da44..10119d9ef4b1 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -44,6 +44,7 @@ Required properties:
 	* "fsl,ls1046a-clockgen"
 	* "fsl,ls1088a-clockgen"
 	* "fsl,ls2080a-clockgen"
+	* "fsl,lx2160a-clockgen"
 	Chassis-version clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 2fe245ca816a..b371b8b20e03 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -203,6 +203,26 @@ EXAMPLE
 
 
 =====================================================================
+Secure memory (SM) Node
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,imx6q-caam-sm"
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two SM parameters:  an offset from
+          the parent physical address and the length the SM registers.
+
+EXAMPLE
+  caam_sm: caam-sm@100000 {
+    compatible = "fsl,imx6q-caam-sm";
+    reg = <0x100000 0x4000>;
+  };
+
+=====================================================================
 Run Time Integrity Check (RTIC) Node
 
   Child node of the crypto node.  Defines a register space that
@@ -366,6 +386,79 @@ EXAMPLE
 	};
 
 =====================================================================
+CAAM SNVS Node
+  Load the SECVIO node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,imx6q-caam-snvs".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC4 configuration
+          registers.
+
+=====================================================================
+Security Violation (SECVIO) Node
+  Reports security violations.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,imx6q-caam-secvio".
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+  - jtag-tamper
+       Usage: optional-but-recommended
+       Value type: <string>
+       Definition:
+           Security tamper on the JTAG
+           Must include "enabled" to enable.
+
+  - watchdog-tamper
+       Usage: optional-but-recommended
+       Value type: <string>
+       Definition:
+           Security tamper on the watchdog
+           Must include "enabled" to enable.
+
+  - internal-boot-tamper
+       Usage: optional-but-recommended
+       Value type: <string>
+       Definition:
+           Security tamper on the internal boot
+           Must include "enabled" to enable.
+
+  - external-pin-tamper
+       Usage: optional-but-recommended
+       Value type: <string>
+       Definition:
+           Security tamper on the external pin
+           Must include "enabled" to enable.
+
+EXAMPLE
+	irq_sec_vio: caam_secvio {
+		compatible = "fsl,imx6q-caam-secvio";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		jtag-tamper = "disabled";
+		watchdog-tamper = "enabled";
+		internal-boot-tamper = "enabled";
+		external-pin-tamper = "disabled";
+	};
+
+
+=====================================================================
 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
 
   A SNVS child node that defines SNVS LP RTC.
@@ -394,18 +487,14 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
 	value type: <u32>
 	Definition: LP register offset. default it is 0x34.
 
-   - clocks
-      Usage: optional, required if SNVS LP RTC requires explicit
-          enablement of clocks
-      Value type: <prop_encoded-array>
-      Definition:  a clock specifier describing the clock required for
-          enabling and disabling SNVS LP RTC.
-
-   - clock-names
-      Usage: optional, required if SNVS LP RTC requires explicit
-          enablement of clocks
-      Value type: <string>
-      Definition: clock name string should be "snvs-rtc".
+  - clocks
+      Usage: optional
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the source clock for
+	  snvs register access. If i.MX clk driver defines the clock node,
+	  it needs user to specify the clocks in device tree for all modules
+	  with snvs LP/HP registers access. The modules involved snvs LP/HP
+	  registers access are snvs-power key, snvs-rtc, and caam.
 
 EXAMPLE
 	sec_mon_rtc_lp@1 {
@@ -550,4 +639,18 @@ FULL EXAMPLE
 		};
 	};
 
+	caam_snvs: caam-snvs@30370000 {
+		compatible = "fsl,imx6q-caam-snvs";
+		reg = <0x30370000 0x10000>;
+	};
+
+	irq_sec_vio: caam_secvio {
+		compatible = "fsl,imx6q-caam-secvio";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		jtag-tamper = "disabled";
+		watchdog-tamper = "enabled";
+		internal-boot-tamper = "enabled";
+		external-pin-tamper = "disabled";
+	};
+
 =====================================================================
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 94c0f8bf4deb..8e069adfa066 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -12,9 +12,42 @@ Required properties:
 - reg : Offset and length of the register set for this device
 - interrupts : Interrupt tuple for this device
 
-Optional properties:
+Clocking information is must for flexcan. please refer below info for
+understanding clocking in flexcan:
+
+• The FLEXCAN module is divided into two blocks. Controller host interface
+  ("CHI") and Protocol Engine ("PE")
+• Both these blocks require clock.
+• CHI is responsible for registers read write including MB read/write.
+  While PE is responsible for Transfer/receive data on CAN bus.
+• The clocks feeding to these two blocks can be synchronous (i.e. same clock)
+  or asynchronous (i.e. separate clocks).
+• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register.
+  - CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE
+  - CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE
+                 clock is not used.
+• If this bit is not implemented in SOC, then SOC only supports asynchronous
+  clocks.
+• Either of the clock can be generated by any of the clock source.
+• When the two clocks are asynchronous, then following restrictions apply to
+  PE clock.
+  - PE clock must be less than CHI clock.
+• If low jitter is required on CAN bus, dedicated oscillator can be used to
+  provide PE clock, but it must be less than CHI clock.
+
+Base on above information clocking info in flexcan can be defined in two ways:
+
+Method 1(Preferred):
+  - clocks: phandle to the clocks feeding the flexcan. Two can be given:
+    - "ipg": Protocol Engine clock
+    - "per": Controller host interface clock
+  - clock-names: Must contain the clock names described just above.
 
-- clock-frequency : The oscillator frequency driving the flexcan device
+Method 2(Not Preferred):
+  - clock-frequency : The synchronous clock frequency supplied to both
+  Controller host interface and Protocol Engine
+
+Optional properties:
 
 - xceiver-supply: Regulator that powers the CAN transceiver
 
@@ -51,3 +84,12 @@ Example:
 		clock-frequency = <200000000>; // filled in by bootloader
 		fsl,clk-source = <0>; // select clock source 0 for PE
 	};
+
+	can@2180000 {
+		compatible = "fsl,lx2160ar1-flexcan";
+		reg = <0x0 0x2180000 0x0 0x10000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk>, <&clockgen 4 7>;
+		clock-names = "ipg", "per";
+		status = "disabled";
+	};
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..8906f8d6efd5 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -38,6 +38,15 @@ Optional properties:
   The regulator will be enabled when initializing the PCIe host and
   disabled either as part of the init process or when shutting down the
   host.
+- ext_osc: use the external oscillator as ref clock( 1: external OSC is
+  used, 0 internal PLL is used).
+- hard_wired: the PCIe port is hard wired to the EP device(0: one slot
+  is connected).
+- reserved-region: one reserved no-map memory used by PCIe EP/RC
+  validation system.
+- interrupt-names: Optional include the following entries:
+	- "dma": The interrupt that is asserted when an DMA interrupter
+	is received
 
 Additional required properties for imx6sx-pcie:
 - clock names: Must include the following additional entries:
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index e20ceaab9b38..99a386ea691c 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -21,6 +21,7 @@ Required properties:
         "fsl,ls1046a-pcie"
         "fsl,ls1043a-pcie"
         "fsl,ls1012a-pcie"
+        "fsl,ls1028a-pcie"
   EP mode:
 	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
 - reg: base addresses and lengths of the PCIe controller register blocks.